1. Field of the Invention
The present invention relates to a non-volatile ferroelectric cell array block having a hierarchy bit-line architecture, and more particularly, to non-volatile ferroelectric cell array block having a hierarchy transfer sensing architecture, in which during a cell data sensing operation, the capacitance of a respective sub bit-line is independent of the capacitance of a main bit-line so that cell sensing capacitance is limited to the capacitance of the sub bit-line.
2. Description of the Background Art
The ferroelectric memory, i.e., a FeRAM (Ferroelectric Random Access Memory), is paid a lot of attention as a next generation memory because it has a data processing speed similar to that of a DRAM (Dynamic Random Access Memory) and also is capable of preserving stored data even when the power is off.
FeRAM is a memory device having a structure very similar to DRAM, and uses capacitors made of a ferroelectric material to benefit a high remanent polarization characteristic of the ferroelectric material. Due to the remanent polarization of the ferroelectric capacitor, data stored in an FRAM memory cell is not erased even if the electric field applied to the memory cell is removed.
Recently, capacity of the nonvolatile ferroelectric memory has increased up to mega-bytes(Mb) or giga-bytes(Gb). However, as a cell size becomes smaller with the increase of capacity, cell capacitance is also reduced.
Although the bit line capacitance should be reduced for a memory with a small cell capacitance to operate more stably, it is not easy to realize this especially in the case of a high integration memory.